The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2008
Filed:
Apr. 10, 2007
Huiling Shang, Yorktown Heights, NY (US);
Meikei Ieong, Wappingers Falls, NY (US);
Jack Oon Chu, Manhasset, NY (US);
Kathryn W. Guarini, Yorktown Heights, NY (US);
Huiling Shang, Yorktown Heights, NY (US);
Meikei Ieong, Wappingers Falls, NY (US);
Jack Oon Chu, Manhasset, NY (US);
Kathryn W. Guarini, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.