The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2008
Filed:
Jun. 02, 2006
OM P. Agrawal, Los Altos, CA (US);
Xiaojie He, Austin, TX (US);
Sajitha Wijesuriya, Macungie, PA (US);
Barry Britton, Orefield, PA (US);
Ming H. Ding, San Jose, CA (US);
Jun Zhao, Allentown, PA (US);
Om P. Agrawal, Los Altos, CA (US);
Xiaojie He, Austin, TX (US);
Sajitha Wijesuriya, Macungie, PA (US);
Barry Britton, Orefield, PA (US);
Ming H. Ding, San Jose, CA (US);
Jun Zhao, Allentown, PA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.