The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2008
Filed:
Dec. 06, 2004
Applicants:
Taber H. Smith, Fremont, CA (US);
Vikas Mehrotra, Fremont, CA (US);
David White, Cambridge, MA (US);
Inventors:
Taber H. Smith, Fremont, CA (US);
Vikas Mehrotra, Fremont, CA (US);
David White, Cambridge, MA (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
Published as:
WO03104921A2; AU2003274370A1; AU2003274370A8; WO03104921A3; EP1532670A2; US2005132306A1; EP1532670A4; US7383521B2; US2009031261A1; US8001516B2;
Smith, Taber. (2008). Characterization and reduction of variation for integrated circuits (U.S. Patent No. 7383521). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7383521
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile