The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2008
Filed:
Aug. 29, 2007
Eric M. Coker, Burlington, VT (US);
Douglas D. Coolbaugh, Essex Junction, VT (US);
Ebenezer E. Eshun, Essex Junction, VT (US);
Zhong-xiang He, Essex Junction, VT (US);
Matthew D. Moon, Jeffersonville, VT (US);
Anthony K. Stamper, Williston, VT (US);
Eric M. Coker, Burlington, VT (US);
Douglas D. Coolbaugh, Essex Junction, VT (US);
Ebenezer E. Eshun, Essex Junction, VT (US);
Zhong-Xiang He, Essex Junction, VT (US);
Matthew D. Moon, Jeffersonville, VT (US);
Anthony K. Stamper, Williston, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.