The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2008

Filed:

Mar. 29, 2005
Applicants:

Hao-yu Chen, Kaohsiung, TW;

Chang-yun Chang, Taipei, TW;

Di-hong Lee, Austin, TX (US);

Fu-liang Yang, Hsin-Chu, TW;

Inventors:

Hao-Yu Chen, Kaohsiung, TW;

Chang-Yun Chang, Taipei, TW;

Di-Hong Lee, Austin, TX (US);

Fu-Liang Yang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/01 (2006.01); H01L 27/12 (2006.01); H01L 31/392 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.


Find Patent Forward Citations

Chen, Hao-Yu. (2008). Fully depleted soi multiple threshold voltage application (U.S. Patent No. 7382023). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7382023

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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