The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2008
Filed:
Mar. 14, 2006
Gregory S. Spencer, Pflugerville, TX (US);
Peter J. Beckage, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Veer Dhandapani, Round Rock, TX (US);
Gregory S. Spencer, Pflugerville, TX (US);
Peter J. Beckage, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Veer Dhandapani, Round Rock, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor process and apparatus provide a planarized hybrid substrate () having a more uniform polish surface () by thickening an SOI semiconductor layer () in relation to a previously or subsequently formed epitaxial silicon layer () with a selective silicon deposition process that covers the SOI semiconductor layer () with a crystalline semiconductor layer (). By forming first gate electrodes () over a first SOI substrate () using deposited (100) silicon and forming second gate electrodes () over an epitaxially grown (110) silicon substrate (), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes () having improved hole mobility.