The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2008
Filed:
Sep. 26, 2005
Henry Law, Los Altos, CA (US);
Brad Sharpe-geisler, San Jose, CA (US);
Giap Tran, San Jose, CA (US);
Kiet Truong, San Jose, CA (US);
Bai Nguyen, Union City, CA (US);
Henry Law, Los Altos, CA (US);
Brad Sharpe-Geisler, San Jose, CA (US);
Giap Tran, San Jose, CA (US);
Kiet Truong, San Jose, CA (US);
Bai Nguyen, Union City, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PLD's programmable logic blocks. The internal power supply powers down the programmable logic blocks in response to the assertion of a power-down signal.