The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2008
Filed:
May. 06, 2004
Richard J. Luyken, München, DE;
Franz Hofmann, München, DE;
Lothar Risch, Neubiberg, DE;
Dirk Manger, Dresden, DE;
Wolfgang Rösner, Ottobrunn, DE;
Till Schlösser, Dresden, DE;
Michael Specht, München, DE;
Richard J. Luyken, München, DE;
Franz Hofmann, München, DE;
Lothar Risch, Neubiberg, DE;
Dirk Manger, Dresden, DE;
Wolfgang Rösner, Ottobrunn, DE;
Till Schlösser, Dresden, DE;
Michael Specht, München, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.