The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2008
Filed:
Jul. 13, 2004
Hong Lin, Vancouver, WA (US);
Wai Lo, Lake Oswego, OR (US);
Sey-shing Sun, Portland, OR (US);
Richard Carter, Fairview, OR (US);
Hong Lin, Vancouver, WA (US);
Wai Lo, Lake Oswego, OR (US);
Sey-Shing Sun, Portland, OR (US);
Richard Carter, Fairview, OR (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of forming a metal gate in a wafer. PolySiGeand polysilicon are used to form a tapered groove. Gate oxide, PolySiGe, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySiGe, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySGe, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySiGe, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.