The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2008
Filed:
Dec. 14, 2005
Akira Goda, Yokohama, JP;
Riichiro Shirota, Fujisawa, JP;
Kazuhiro Shimizu, Yokohama, JP;
Hiroaki Hazama, Hachioji, JP;
Hirohisa Iizuka, Yokohama, JP;
Seiichi Aritome, Yokohama, JP;
Wakako Moriyama, Yokohama, JP;
Akira Goda, Yokohama, JP;
Riichiro Shirota, Fujisawa, JP;
Kazuhiro Shimizu, Yokohama, JP;
Hiroaki Hazama, Hachioji, JP;
Hirohisa Iizuka, Yokohama, JP;
Seiichi Aritome, Yokohama, JP;
Wakako Moriyama, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki-shi, JP;
Abstract
A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.