The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 2008

Filed:

Jun. 22, 2004
Applicants:

Naveen Cherukuri, San Jose, CA (US);

Tim Frodsham, Portland, OR (US);

Eduard Roytman, Brookline, MA (US);

Sanjay Dabral, Palo Alto, CA (US);

Rahul Shah, Marlborough, MA (US);

Theodore Z. Schoenborn, Portland, OR (US);

Maurice B. Steinman, Marlborough, MA (US);

David S. Dunning, Portland, OR (US);

Inventors:

Naveen Cherukuri, San Jose, CA (US);

Tim Frodsham, Portland, OR (US);

Eduard Roytman, Brookline, MA (US);

Sanjay Dabral, Palo Alto, CA (US);

Rahul Shah, Marlborough, MA (US);

Theodore Z. Schoenborn, Portland, OR (US);

Maurice B. Steinman, Marlborough, MA (US);

David S. Dunning, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 7/216 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatuses for determining clock failure for a multi-agent system employing a link-based interconnection scheme using a forwarded clock. For one embodiment of the invention, the cessation of the forwarded clock initiates a clock failure determination process. For one embodiment of the invention, upon a determination of clock failure, an alternate clock lane is implemented using a pre-designated data lane.


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