The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 15, 2008

Filed:

Jul. 29, 2005
Applicants:

Daniel Wang, San Jose, CA (US);

Chunchieh Huang, Fremont, CA (US);

Dong Jun Kim, San Jose, CA (US);

Inventors:

Daniel Wang, San Jose, CA (US);

Chunchieh Huang, Fremont, CA (US);

Dong Jun Kim, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/425 (2006.01);
U.S. Cl.
CPC ...
Abstract

Substrate isolation trench () are formed in a semiconductor substrate (). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric () faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.


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