Sram cell design to improve stability

Abstract

A novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions. Both methods improve stability by eliminating half-select mode and facilitate rail to rail data transfer in and out of the SRAM cell without disturbing the other cells.