The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2008
Filed:
Sep. 08, 2005
Chih-wei Lin, Hsinchu, TW;
Hong-hsing Chou, Taipei, TW;
Yeh-jye Wang, Hsinchu, TW;
Chen-fu Chien, Hsinchu, TW;
Jen-hsin Wang, Sindian, TW;
Chih-wei Hsiao, Taipei, TW;
Chih-Wei Lin, Hsinchu, TW;
Hong-Hsing Chou, Taipei, TW;
Yeh-Jye Wang, Hsinchu, TW;
Chen-Fu Chien, Hsinchu, TW;
Jen-Hsin Wang, Sindian, TW;
Chih-Wei Hsiao, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.