The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2008
Filed:
Aug. 31, 2004
Huilong Zhu, Poughkeepsie, NY (US);
Bruce B. Doris, Brewster, NY (US);
Xinlin Wang, Poughkeepsie, NY (US);
Jochen Beintner, Wappingers Falls, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
Philip J. Oldiges, LaGrangeville, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
Bruce B. Doris, Brewster, NY (US);
Xinlin Wang, Poughkeepsie, NY (US);
Jochen Beintner, Wappingers Falls, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
Philip J. Oldiges, LaGrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.