The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2008
Filed:
Jun. 16, 2006
Yasuhiko Honda, Yokohama, JP;
Hideo Kato, Kawasaki, JP;
Hidetoshi Saito, Yokohama, JP;
Masao Kuriyama, Fujisawa, JP;
Tokumasa Hara, Yokohama, JP;
Takafumi Ikeda, Yokohama, JP;
Tatsuya Hiramatsu, Yokohama, JP;
Yasuhiko Honda, Yokohama, JP;
Hideo Kato, Kawasaki, JP;
Hidetoshi Saito, Yokohama, JP;
Masao Kuriyama, Fujisawa, JP;
Tokumasa Hara, Yokohama, JP;
Takafumi Ikeda, Yokohama, JP;
Tatsuya Hiramatsu, Yokohama, JP;
Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;
Abstract
A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supply potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.