The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2008
Filed:
Jun. 24, 2005
Brad Sharpe-geisler, San Jose, CA (US);
OM P. Agrawal, Los Altos, CA (US);
Kiet Truong, San Jose, CA (US);
Giap Tran, San Jose, CA (US);
Bai Nguyen, Union City, CA (US);
Brad Sharpe-Geisler, San Jose, CA (US);
Om P. Agrawal, Los Altos, CA (US);
Kiet Truong, San Jose, CA (US);
Giap Tran, San Jose, CA (US);
Bai Nguyen, Union City, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.