The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2008
Filed:
Feb. 13, 2006
Tetsuya Nitta, Tokyo, JP;
Yasunori Yamashita, Tokyo, JP;
Shinichiro Yanagi, Tokyo, JP;
Fumitoshi Yamamoto, Tokyo, JP;
Tetsuya Nitta, Tokyo, JP;
Yasunori Yamashita, Tokyo, JP;
Shinichiro Yanagi, Tokyo, JP;
Fumitoshi Yamamoto, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an ntype semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.