The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2008
Filed:
Jul. 14, 2003
Sudhakar Kale, San Jose, CA (US);
Amit Chowdhary, Sunnyvale, CA (US);
Phani Saripella, Santa Clara, CA (US);
Naresh K. Sehgal, Santa Clara, CA (US);
Rajesh Gupta, Santa Clara, CA (US);
Sudhakar Kale, San Jose, CA (US);
Amit Chowdhary, Sunnyvale, CA (US);
Phani Saripella, Santa Clara, CA (US);
Naresh K. Sehgal, Santa Clara, CA (US);
Rajesh Gupta, Santa Clara, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.