The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7335982 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 26, 2008

Filed:

Mar. 30, 2005
Applicants:

Chin-li Kao, Penghu County, TW;

Yi-shao Lai, Taipei County, TW;

Jeng-da Wu, Kaohsiung, TW;

Tong-hong Wang, Selangor D. E., MY;

Inventors:

Chin-Li Kao, Penghu County, TW;

Yi-Shao Lai, Taipei County, TW;

Jeng-Da Wu, Kaohsiung, TW;

Tong-Hong Wang, Selangor D. E., MY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.


Find Patent Forward Citations

Kao, Chin-Li. (2008). Chip package structure and chip packaging process (U.S. Patent No. 7335982). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7335982

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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