The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2008

Filed:

Aug. 27, 2004
Applicants:

John Chen, Shanghai, CN;

Roger Lee, Shanghai, CN;

Inventors:

John Chen, Shanghai, CN;

Roger Lee, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is overlying the surface region. A gate polysilicon layer is overlying the gate dielectric layer. A mask layer is overlying the gate polysilicon layer. The device also has a gate electrode formed within the gate polysilicon layer. The gate electrode has a first predetermined width and a first predetermined thickness. Preferably, the gate electrode has a first side and a second side formed between the first predetermined width. The gate electrode is coupled to the double diffused drain region within the well region. Preferably, the first side has a lower corner overlying the gate dielectric layer and an upper corner underlying the mask layer and the second side has a lower corner overlying the gate dielectric layer and an upper corner underlying the mask layer. A first insulating region formed from polysilicon is formed at the lower corner on the first side of the gate electrode. The first insulating region extends from the first side toward a first preselect region within the gate electrode. A second insulating region formed from polysilicon material is at the lower corner on the second side of the gate electrode. The second insulating region extends from the second side toward a second preselected region within the gate electrode. A second predetermined width is formed between the first preselect region and the second preselected region. The second predetermined width comprises substantially polysilicon material. Preferably, the high voltage device has a breakdown voltage of the high voltage semiconductor device is characterized by a voltage of greater than 20 volts.


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