The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2008
Filed:
Nov. 04, 2004
Yoichi Matsumura, Takatsuki, JP;
Takako Ohashi, Otsu, JP;
Katsuya Fujimura, Kameoka, JP;
Chihiro Itoh, Nagaokakyo, JP;
Hiroki Taniguchi, Kyoto, JP;
Yoichi Matsumura, Takatsuki, JP;
Takako Ohashi, Otsu, JP;
Katsuya Fujimura, Kameoka, JP;
Chihiro Itoh, Nagaokakyo, JP;
Hiroki Taniguchi, Kyoto, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cellon the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.