The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2008
Filed:
Jun. 04, 2004
Takashi Kikuchi, Inagi, JP;
Ryosuke Kimoto, Hamura, JP;
Hiroshi Kawakubo, Fussa, JP;
Takashi Miwa, Fussa, JP;
Chikako Imura, Higashiyamato, JP;
Takafumi Nishita, Iruma, JP;
Hiroshi Koyama, Tachikawa, JP;
Masanori Shibamoto, Saitama, JP;
Masaru Kawakami, Machida, JP;
Takashi Kikuchi, Inagi, JP;
Ryosuke Kimoto, Hamura, JP;
Hiroshi Kawakubo, Fussa, JP;
Takashi Miwa, Fussa, JP;
Chikako Imura, Higashiyamato, JP;
Takafumi Nishita, Iruma, JP;
Hiroshi Koyama, Tachikawa, JP;
Masanori Shibamoto, Saitama, JP;
Masaru Kawakami, Machida, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.