The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Jun. 28, 2005
Neeraj Kaul, Fremont, CA (US);
Balkrishna Rashingkar, San Jose, CA (US);
Anthony Y. Tseng, Bellevue, WA (US);
Wei-chih Tseng, Fremont, CA (US);
Neeraj Kaul, Fremont, CA (US);
Balkrishna Rashingkar, San Jose, CA (US);
Anthony Y. Tseng, Bellevue, WA (US);
Wei-Chih Tseng, Fremont, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A system that routes nets within an integrated circuit. During operation, the system receives a representation for the integrated circuit, which includes block boundaries for physical partitions of the IC generated from a hierarchical design placement of the integrated circuit. The system then classifies each net in the integrated circuit based on the location of pins associated with the net. Next, the system generates routing constraints for each net based on the classification of the net and applies a feedthrough constraint to the physical partitions to restrict nets from feeding through physical partition boundaries. Finally, the system routes each net using the routing constraints for the net and the feedthrough constraints for the physical partitions. This routing is performed based on these block boundaries prior to finalizing the hierarchical design placement, thereby facilitating early detection of congestion or timing violations which can be corrected early in the design process.