The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2007

Filed:

Nov. 29, 2005
Applicants:

Wayne F. Ellis, Jericho, VT (US);

Randy W. Mann, Poughquag, NY (US);

David J. Wager, Jericho, VT (US);

Robert C. Wong, Poughkeepsie, NY (US);

Inventors:

Wayne F. Ellis, Jericho, VT (US);

Randy W. Mann, Poughquag, NY (US);

David J. Wager, Jericho, VT (US);

Robert C. Wong, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A static random access memory ('SRAM') is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.


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