The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Jul. 08, 2005
Gurkan Ilicali, Munich, DE;
Richard Johannes Luyken, Munich, DE;
Wolfgang Roesner, Ottobrunn, DE;
Infineon Technologies AG, , DE;
Abstract
The invention relates to a process for producing a layer arrangement, in which, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate, a first semiconductor layer is formed on the sacrificial layer, a first electrically insulating layer is formed on the first semiconductor layer, an electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned, the first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer, a substrate is secured over the patterned electrically conductive layer, material of the auxiliary substrate is removed, so that the sacrificial layer is uncovered, the sacrificial layer is selectively removed, so as to form a trench, and a second electrically insulating layer is formed in the trench, then an electrically conductive structure is formed on this second electrically insulating layer.