The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2007

Filed:

Feb. 07, 2007
Applicants:

Naoki Yada, Sayama, JP;

Eiichi Ishikawa, Higashimurayama, JP;

Inventors:

Naoki Yada, Sayama, JP;

Eiichi Ishikawa, Higashimurayama, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its processing. An erase and program control program for an electrically erasable and programmable non-volatile memory is configured inclusive of a loop of the application of a high voltage pulse and data verify or the like, for example. If a program jumped to a subroutine for an address specified by a user is programmed in advance during this loop, then a process by a CPU can be temporarily jumped to the subroutine for the user defined address. Thus, erase and programming can be effected on a system which needs to confirm internal and external events every predetermined intervals or a system with a learning function, or the like during the execution of a user program.


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