The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2007
Filed:
Jul. 07, 2005
Rath Ung, Apex, NC (US);
Jan Zieleman, Cary, NC (US);
Robert Perry, Cary, NC (US);
Norbert Rehm, Apex, NC (US);
Dirk Fuhrmann, Alex, NC (US);
Rath Ung, Apex, NC (US);
Jan Zieleman, Cary, NC (US);
Robert Perry, Cary, NC (US);
Norbert Rehm, Apex, NC (US);
Dirk Fuhrmann, Alex, NC (US);
Infineon Technologies, AG, Neubiberg, DE;
Abstract
A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer chip under test is assigned a unique programmable identification. Once each chip has been assigned a corresponding identification, the chips may each be individually accessible by that identification to provide parameter values to chip registers to configure that chip. The configured chips may be subsequently tested in parallel to evaluate the parameter settings. In addition, the present invention enables chips to share data I/O pins or lines, thereby reducing the quantity of testing machine pins utilized for each chip and enabling a greater quantity of chips to be tested in a parallel fashion.