The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7298459 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 20, 2007

Filed:

Jul. 15, 2005
Applicants:

Santiago E. Del Puerto, Milton, NY (US);

Stephen Roux, New Fairfield, CT (US);

Justin L. Kreuzer, Trumbull, CT (US);

Inventors:

Santiago E. del Puerto, Milton, NY (US);

Stephen Roux, New Fairfield, CT (US);

Justin L. Kreuzer, Trumbull, CT (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03B 27/32 (2006.01); G03B 27/58 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method utilizing a lithography system comprises a lithography patterning chamber, a wafer exchange chamber separated from the lithography patterning chamber by a first gate valve, and at least one alignment load-lock separated from the wafer exchange chamber by a second gate valve. The alignment load-lock includes an alignment stage that aligns a wafer during pump-down. The alignment load-lock can be uni-directional or bi-directional. The lithography system can include one or multiple alignment load-locks.


Find Patent Forward Citations

del Puerto, Santiago. (2007). Wafer handling method for use in lithography patterning (U.S. Patent No. 7298459). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7298459

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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