The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2007
Filed:
Mar. 16, 2005
Huajie Chen, Danbury, CT (US);
Dureseti Chidambarrao, Weston, CT (US);
Oleg G. Gluschenkov, Poughkeepsie, NY (US);
An L. Steegen, Stamford, CT (US);
Haining S. Yang, Wappingers Falls, NY (US);
Huajie Chen, Danbury, CT (US);
Dureseti Chidambarrao, Weston, CT (US);
Oleg G. Gluschenkov, Poughkeepsie, NY (US);
An L. Steegen, Stamford, CT (US);
Haining S. Yang, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.