The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2007
Filed:
May. 04, 2004
Yue-song He, San Jose, CA (US);
Richard Fastow, Cupertino, CA (US);
Takao Akaogi, Cupertino, CA (US);
Wing Leung, Palo Alto, CA (US);
Zhigang Wang, Sunnyvale, CA (US);
Yue-Song He, San Jose, CA (US);
Richard Fastow, Cupertino, CA (US);
Takao Akaogi, Cupertino, CA (US);
Wing Leung, Palo Alto, CA (US);
Zhigang Wang, Sunnyvale, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.