The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2007
Filed:
Nov. 04, 2005
Lawrence T. Pileggi, Pittsburgh, PA (US);
Andrzej J. Strojwas, Pittsburgh, PA (US);
Lucio L. Lanza, Palo Alto, CA (US);
Lawrence T. Pileggi, Pittsburgh, PA (US);
Andrzej J. Strojwas, Pittsburgh, PA (US);
Lucio L. Lanza, Palo Alto, CA (US);
PDF Solutions, Inc., San Jose, CA (US);
Abstract
The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.