The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2007
Filed:
Aug. 05, 2005
Jong-hyuk Kim, Incheon-si, KR;
Soon-moon Jung, Yongin-si, KR;
Won-seok Cho, Suwon-si, KR;
Jae-hoon Jang, Hwaseong-si, KR;
Kun-ho Kwak, Yongin-si, KR;
Sung-jin Kim, Hwaseong-si, KR;
Jae-joo Shim, Gyeonggi-do, KR;
Jong-Hyuk Kim, Incheon-si, KR;
Soon-Moon Jung, Yongin-si, KR;
Won-Seok Cho, Suwon-si, KR;
Jae-Hoon Jang, Hwaseong-si, KR;
Kun-Ho Kwak, Yongin-si, KR;
Sung-Jin Kim, Hwaseong-si, KR;
Jae-Joo Shim, Gyeonggi-do, KR;
Abstract
Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.