The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2007
Filed:
Sep. 09, 2003
Howard T. Barrett, Starksboro, VT (US);
Pierre J. Bouchard, South Burlington, VT (US);
James B. Clairmont, Williston, VT (US);
Karen S. Edwards, Milton, VT (US);
Maureen F. Mcfadden, Burlington, VT (US);
John F. Rudden, Jr., Georgia, VT (US);
Florence Marie St. Pierre Sears, Crown Point, NY (US);
Jeffrey C. Stamm, Colchester, VT (US);
Howard T. Barrett, Starksboro, VT (US);
Pierre J. Bouchard, South Burlington, VT (US);
James B. Clairmont, Williston, VT (US);
Karen S. Edwards, Milton, VT (US);
Maureen F. McFadden, Burlington, VT (US);
John F. Rudden, Jr., Georgia, VT (US);
Florence Marie St. Pierre Sears, Crown Point, NY (US);
Jeffrey C. Stamm, Colchester, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in the chip. The total cycle time for mask manufacturing is reduced because kerf build is accomplished prior to start of the mask manufacturing process. Also provided is the use of load balancing across multiple servers during kerf and chip design to optimize computing resources.