Memory circuit comprising an error correcting code

Abstract

A memory circuit with an error correcting system comprising an address bus (), an input data bus (), and an output data bus (), the circuit comprising a memory having an address bus (), a data bus () and an error correcting circuit comprising an encoder (). A first address register () is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register () is connected to the input data bus of the circuit () for storing data transmitted to the encoder (). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.