The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2007
Filed:
Dec. 16, 2005
Tuo-hung Ho, Chia-Yi, TW;
Ming-fang Wang, Taichung, TW;
Chi-chun Chen, Kaohsiung, TW;
Chih-wei Yang, Kaohsiung, TW;
Liang-gi Yao, Hsing-Chu, TW;
Chih-chang Chen, Taoyuan, TW;
Tuo-Hung Ho, Chia-Yi, TW;
Ming-Fang Wang, Taichung, TW;
Chi-Chun Chen, Kaohsiung, TW;
Chih-Wei Yang, Kaohsiung, TW;
Liang-Gi Yao, Hsing-Chu, TW;
Chih-Chang Chen, Taoyuan, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.