The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2007
Filed:
Jun. 27, 2006
Jean Audet, Granby, CA;
Louis B. Capps, Jr., Georgetown, TX (US);
Glenn G. Daves, Fishkill, NY (US);
Joanne Ferris, Essex, VT (US);
Anand Haridass, Austin, TX (US);
Ronald E. Newhart, Essex Junction, VT (US);
Michael J. Shapiro, Austin, TX (US);
Jean Audet, Granby, CA;
Louis B. Capps, Jr., Georgetown, TX (US);
Glenn G. Daves, Fishkill, NY (US);
Joanne Ferris, Essex, VT (US);
Anand Haridass, Austin, TX (US);
Ronald E. Newhart, Essex Junction, VT (US);
Michael J. Shapiro, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.