The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2007

Filed:

Oct. 25, 2004
Applicants:

Inki Kim, Seoul, KR;

Sang Yeon Kim, Chungcheng-bukdo, KR;

Min Paek, Heungduck-gu Chongju, KR;

Chiew Sin Ping, Kuala Lumpur, MY;

Wan Gie Lee, Namyangju-si, KR;

Choong Shiau Chien, Penang, MY;

Zadig Lam, Singapore, SG;

Hitomi Watanabe, Tokyo, JP;

Naoto Inoue, Chiba, JP;

Inventors:

Inki Kim, Seoul, KR;

Sang Yeon Kim, Chungcheng-bukdo, KR;

Min Paek, Heungduck-gu Chongju, KR;

Chiew Sin Ping, Kuala Lumpur, MY;

Wan Gie Lee, Namyangju-si, KR;

Choong Shiau Chien, Penang, MY;

Zadig Lam, Singapore, SG;

Hitomi Watanabe, Tokyo, JP;

Naoto Inoue, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact. Thereafter, a first gate oxide having a first thickness is formed on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure. The first edge is separated from the first isolation structure by a first distance. The second edge is separated from the second isolation structure by a second distance. Thereafter, a second gate oxide having a second thickness is formed on the second active region, the second thickness being different than the first thickness.


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