The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2007
Filed:
Mar. 31, 2005
Won Gi Min, Chandler, AZ (US);
Robert W. Baird, Gilbert, AZ (US);
Jiang-kai Zuo, Chandler, AZ (US);
Gordon P. Lee, Gilbert, AZ (US);
Won Gi Min, Chandler, AZ (US);
Robert W. Baird, Gilbert, AZ (US);
Jiang-Kai Zuo, Chandler, AZ (US);
Gordon P. Lee, Gilbert, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An antifuse element () having end corners () of a gate electrode () positioned directly above an active area () or bottom electrode. The minimum programming voltage between the gate electrode () and the active area () creates a current path through an insulating layer () positioned therebetween. The high electric field created at the end corners () of the gate electrode () results in a breakdown and rupture of the insulating layer () at points directly beneath the end corners (). This localization of the insulating layer () at the corners () provides for lower post program resistance and variation, and faster programming at a lower programming power. The antifuse elements () when integrated into an array () provide for increased packing density. The array is fabricated to include multiple active areas () for individual antifuse element () programming or a common active area () for multi-element programming.