The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2007
Filed:
Dec. 19, 2003
Hiroaki Ohkubo, Kanagawa, JP;
Masayuki Furumiya, Kanagawa, JP;
Ryota Yamamoto, Kanagawa, JP;
Yasutaka Nakashiba, Kanagawa, JP;
Hiroaki Ohkubo, Kanagawa, JP;
Masayuki Furumiya, Kanagawa, JP;
Ryota Yamamoto, Kanagawa, JP;
Yasutaka Nakashiba, Kanagawa, JP;
NEC Electronics Corporation, Kanagawa, JP;
Abstract
A semiconductor IC device includes a base substrate comprising P-type silicon, a first P-type silicon layer is provided on the base substrate, and an N-type silicon layer and a second P-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P-type silicon layer and the N-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N-type silicon layer and the second P-type silicon layer. The first P-type silicon layer is connected to ground potential wiring GND, and the N-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P-type silicon layer and the N-type silicon layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile