The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2007

Filed:

Jun. 15, 2005
Applicants:

David V. Caletka, Apalachin, NY (US);

Varaprasad V. Calmidi, Binghamton, NY (US);

Sanjeev Sathe, San Jose, CA (US);

Inventors:

David V. Caletka, Apalachin, NY (US);

Varaprasad V. Calmidi, Binghamton, NY (US);

Sanjeev Sathe, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for the chip during operation thereof and may operate in combination with other elements to extend the heat paths. Concentric lines also assure sufficient bonding area on the substrate so as to prevent delamination of the chip from the substrate as may occur during high temperatures associated with subsequent processing such as solder ball re-flow. A method of making the package is also provided, as is an information handling system (e.g., computer) adapted for utilizing such packages.


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