The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2007

Filed:

Dec. 23, 2004
Applicants:

Marcos Karnezos, Palo Alto, CA (US);

Flynn Carson, Redwood City, CA (US);

Youngcheol Kim, Young in-si, KR;

Inventors:

Marcos Karnezos, Palo Alto, CA (US);

Flynn Carson, Redwood City, CA (US);

Youngcheol Kim, Young in-si, KR;

Assignee:

ChipPAC, Inc., Fremont, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 21/00 (2006.01); H05K 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.


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