The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2007
Filed:
Jan. 10, 2005
Reza Arghavani, Scotts Valley, CA (US);
Michael Chiu Kwan, Sunnyvale, CA (US);
Li-qun Xia, Santa Clara, CA (US);
Kang Sub Yim, Santa Clara, CA (US);
Reza Arghavani, Scotts Valley, CA (US);
Michael Chiu Kwan, Sunnyvale, CA (US);
Li-Qun Xia, Santa Clara, CA (US);
Kang Sub Yim, Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materials may be silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, or combinations thereof. The deposition is performed in a plasma enhanced chemical vapor deposition chamber and the deposition temperature is less than 450° C. The sidewall spacers so produced provide good capacity resistance, as well as excellent structural stability and hermeticity.