The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2007

Filed:

Jun. 30, 2004
Applicants:

Robert Nickerson, Chandler, AZ (US);

Brian Taggart, Phoenix, AZ (US);

Hai Ding, Shanghai, CN;

Inventors:

Robert Nickerson, Chandler, AZ (US);

Brian Taggart, Phoenix, AZ (US);

Hai Ding, Shanghai, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wire-bonding substrate includes a curvilinear wire-bond pad. The curvilinear wire-bond pad is used in reverse wire bonding to couple a die with the substrate. A curvilinear wire-bond pad is also disclosed that is located directly above the via in the substrate. A wire-bonding substrate includes a first wire-bond pad and a first via that is disposed directly below the first wire-bond pad in the wire-bonding substrate. A package is includes a chip stack with a total die-side characteristic dimension, and a total substrate-side characteristic dimension that is smaller than the total die-side characteristic dimension. A computing system includes the curvilinear wire-bond pad.


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