The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2007
Filed:
Aug. 02, 2004
Lap Chan, Singapore, SG;
Sanford Chu, Singapore, SG;
Chit Hwei NG, Singapore, SG;
Purakh Verma, Singapore, SG;
Jia Zhen Zheng, Singapore, SG;
Johnny Chew, Singapore, SG;
Choon Beng Sia, Singapore, SG;
Lap Chan, Singapore, SG;
Sanford Chu, Singapore, SG;
Chit Hwei Ng, Singapore, SG;
Purakh Verma, Singapore, SG;
Jia Zhen Zheng, Singapore, SG;
Johnny Chew, Singapore, SG;
Choon Beng Sia, Singapore, SG;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
A first method of reducing semiconductor device substrate effects comprising the following steps. Oor Oare selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.