The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2007
Filed:
Dec. 15, 2005
Rajat Goel, Santa Clara, CA (US);
Edgardo F. Klass, Palo Alto, CA (US);
Andrew J. Demas, Los Altos, CA (US);
Shih-chieh Wen, San Jose, CA (US);
Honkai Tam, Redwood City, CA (US);
Rajat Goel, Santa Clara, CA (US);
Edgardo F. Klass, Palo Alto, CA (US);
Andrew J. Demas, Los Altos, CA (US);
Shih-Chieh Wen, San Jose, CA (US);
Honkai Tam, Redwood City, CA (US);
P.A. Semi, Inc., Santa Clara, CA (US);
Abstract
In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.