The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2007
Filed:
Jul. 08, 2004
Inkuk Kang, San Jose, CA (US);
Hiroyuki Kinoshita, Sunnyvale, CA (US);
Boon-yong Ang, Cupertino, CA (US);
Hajime Wada, San Jose, CA (US);
Simon S Chan, Saratoga, CA (US);
Cinti X Chen, Fremont, CA (US);
Inkuk Kang, San Jose, CA (US);
Hiroyuki Kinoshita, Sunnyvale, CA (US);
Boon-Yong Ang, Cupertino, CA (US);
Hajime Wada, San Jose, CA (US);
Simon S Chan, Saratoga, CA (US);
Cinti X Chen, Fremont, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.