The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2007
Filed:
Jan. 11, 2005
Kevin J. Hess, Austin, TX (US);
Susan H. Downey, Austin, TX (US);
James W. Miller, Austin, TX (US);
Cheng Choi Yong, Kuala Lumpur, MY;
Kevin J. Hess, Austin, TX (US);
Susan H. Downey, Austin, TX (US);
James W. Miller, Austin, TX (US);
Cheng Choi Yong, Kuala Lumpur, MY;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.