The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2007

Filed:

Jan. 05, 2005
Applicants:

Bernd Karl-heinz Appelt, Apalachin, NY (US);

James Russell Bupp, Endwell, NY (US);

Donald Seton Farquhar, Endicott, NY (US);

Ross William Keesler, Endicott, NY (US);

Michael Joseph Klodowski, Endicott, NY (US);

Andrew Michael Seman, Kirkwood, NY (US);

Gary Lee Schild, Endicott, NY (US);

Inventors:

Bernd Karl-Heinz Appelt, Apalachin, NY (US);

James Russell Bupp, Endwell, NY (US);

Donald Seton Farquhar, Endicott, NY (US);

Ross William Keesler, Endicott, NY (US);

Michael Joseph Klodowski, Endicott, NY (US);

Andrew Michael Seman, Kirkwood, NY (US);

Gary Lee Schild, Endicott, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps, etching the metal layer exposed by said development to form said plurality of conductive bumps, removing said first photoresist, applying a second photoresist onto the metal layer, exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.


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