The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2007

Filed:

Feb. 24, 2005
Applicants:

Robert J. Allen, Jericho, VT (US);

Peter K. Chan, Union City, CA (US);

Evanthia Papadopoulou, New York, NY (US);

Sarah C. Prue, Richmond, VT (US);

Mervyn Y. Tan, South Burlington, VT (US);

Inventors:

Robert J. Allen, Jericho, VT (US);

Peter K. Chan, Union City, CA (US);

Evanthia Papadopoulou, New York, NY (US);

Sarah C. Prue, Richmond, VT (US);

Mervyn Y. Tan, South Burlington, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 19/00 (2006.01); G06F 17/10 (2006.01); G06F 11/00 (2006.01); G06K 9/03 (2006.01); G06K 9/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.


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